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ok. im in dire need of help. i have 3 final assignments due on monday. final thesis submission, biomedical final assignment and my comp architecture final assignment.
im graduatin at the end of this semester, so there is a heavy load for me. my thesis about radio and electromagnetics antennas took so much out of me the whole semester.
im still preparing for my final presentation this semester. (in 2 days) and doing both assignments listed above as well.
but the thing is, i think i don have enough time.
could someone, anyone.. please help me write a code. its hard to do, but i have no choice but to submit my plea online now. my partner for the comp arch has decided to ditch me at such a critical moment.
i have no code.
the question is stated below. Please note, assignment 3 is a continuation of assignment 2. im posting both questions in just for reference purposes.
Assignment 2
Write a cache simulator to model the cache behaviour when executing the matrix multiply program. Do not extend Assignment 1 to accomplish this.
The following mandatory assumptions apply:
longints are 4 bytes long
Processor
1 nS pipeline clock;
Main Memory
main memory is comprised of 64x64Mx1bit DRAM chips;
the random access time is 50nSec;
the cycle time is 100nSec;
access to the same row is 10nS;
to simplify the problem assume address setup and data transfer time is 0nS;
the memory data bus is 16 bytes (64 bits) wide.
Cache Memory
Direct mapped 2 way set associative with 4096 bytes available for data;
reads or writes to the cache take 25nS; (this is set artificially high for Assig 3)
write through strategy;
the tag data fields can be read from or written to independently;
Perform the simulation for:
8, 16, 32 bytes per cache line
deferred write back
LRU replacement
matrix dimension 3 to 65 in steps of 1
Assignment 3
Extend assignment 2 to determine the performance of the matrix multiply program on the memory hierarchy when running on 1, 2 and 4 processors. The processors share the main memory but have their own caches. The simulation must model the contention when more than one processor accesses memory at a time and in doing so keep track of the total simulated time taken to execute the program for the following conditions as well as those of Assignment 2:
8 bytes per cache line and 512 lines per cache;
reads or writes to the cache take 25nS;
caches are 2 way set associative direct mapped
write through strategy
LRU replacement;
matrix dimension 3 to 65 in steps of 1
Let someone save my skin. please.....
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Hey we can't write whole code for you..u have to do your assignments yourself
if you have any specific problem regarding your code
you can ask for help
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eeeks